tscircuit Checks
https://github.com/tscircuit/checks- Category
- Developer Tools
- Rank
- No. 1634Tools index
- Pricing
- Open Source
- Type
- TOOL
- Builder
- tscircuit
- GitHub
- 4 stars
- Date
About
Validity and Design Rule checks for Circuit JSON. Catch electrical and layout issues in tscircuit designs before fabrication.
What it does
A TypeScript library that accepts circuit element arrays and returns structured errors or warnings. Individual checks target connectivity, geometry, clearances, board boundaries, trace length, pin metadata, connector orientation, and test-point access. Aggregate runners combine those checks by category or across the whole design.
Why it's ranked here
The coverage is unusually concrete: it catches both electrical omissions and physical conflicts, while preserving measured clearance details in specialized diagnostics. It also avoids reporting the same trace-obstacle pair as both an overlap and a near miss. The strongest fit is inside the tscircuit data model, not as a general-purpose PCB checker.
What's good
Checks account for connectivity and shared layers before flagging several spacing violations, reducing obvious false positives. Board-level manufacturing values can override defaults derived from JLCPCB tolerances. Diagnostics often include affected element identifiers, measured values, required limits, and a useful center point. Category runners let callers choose placement, routing, netlist, or pin-specification coverage.
Tradeoffs
The package is tightly coupled to Circuit JSON types and related tscircuit utilities. It exposes a library surface, but the supplied text shows no command-line interface or hosted API. Some behavior is narrower than a full electrical rule system: the netlist aggregate currently checks required-pin connectivity only. Same-net via spacing also contains an explicit note that its pairwise implementation is inefficient.
How to use it well
Use it in TypeScript tooling that already produces Circuit JSON, ideally after routing and before sending a board toward fabrication. Run focused groups during interactive design, then run the complete aggregate in automated validation. It suits tscircuit authors and tool builders who need machine-readable diagnostics. It does not replace a standalone PCB editor, fabrication service, or broad schematic simulator.
Technical notes+
The public exports in index.ts include individual checks, NetManager, dedupePcbDrcErrors, and aggregate runners. lib/run-all-checks.ts composes synchronous checks behind async category functions, then concatenates their results. lib/drc-defaults.ts reads board-specific ManufacturingDrcProperties and falls back to JLCPCB tolerance data. lib/check-pad-trace-clearance.ts keeps the smallest positive gap per pad-trace pair and suppresses clearance output for overlaps; lib/check-via-trace-clearance.ts applies the same classification to vias. lib/check-pad-pad-clearance.ts uses SpatialObjectIndex plus a connectivity map, while lib/check-same-net-via-spacing.ts uses nested via pairs and explicitly notes the inefficiency. package.json defines an ESM package built with tsup and tested with Bun.
Observed
- Primary language
- TypeScript
- Packaging
- ES module package published as @tscircuit/checks, with only built distribution artifacts included
- Install surface
- JavaScript package with peer dependencies on TypeScript, circuit-json, connectivity mapping, geometry, and tscircuit math utilities
- Interface
- Library exports individual checks, category runners, a complete aggregate runner, and connectivity helpers
- Test command
- Bun test
- Build tool
- tsup
Read from README.md, package.json, index.ts, lib/net-manager.ts, lib/drc-defaults.ts, lib/run-all-checks.ts, lib/check-vias-in-pads.ts, lib/dedupe-pcb-drc-errors.ts, lib/check-pad-pad-clearance.ts, lib/check-pcb-trace-lengths.ts, lib/check-via-pad-clearance.ts, lib/check-pad-trace-clearance.ts, lib/check-via-trace-clearance.ts, lib/check-no-power-pin-defined.ts, lib/check-same-net-via-spacing.ts.
What it can do
Validate Circuit JSON syntax and structure
Circuit JSON file → Validation report with syntax errors
Check electrical connectivity rules
tscircuit design file → Electrical rule check report
Verify design rule compliance
Circuit layout data → Design rule violations list
Detect layout issues before fabrication
Circuit design files → Layout issue warnings and errors
Analyze component placement errors
Component placement data → Component placement violation report
Check trace width and spacing compliance
PCB trace layout data → Trace compliance verification results
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