NVIDIA CUDA 13.5 Brings NVIDIA Vera Rubin GA Support

NVIDIA says CUDA Toolkit 13.5 moves support for its Vera Rubin GPU architecture from early developer access to general availability, which its announcement describes as ready for enterprise production. CUDA is the toolkit of compilers, libraries and developer tools that software uses to run on NVIDIA GPUs. Vera Rubin is NVIDIA's successor to Blackwell; its rack-scale system pairs 72 Rubin GPUs with 36 Vera CPUs, as described in Artificial Analysis's first serving benchmarks of that rack. The post does not list what was missing during early access. It does name one compatibility break: Rubin and later GPUs do not support the Tesla Compute Cluster (TCC) driver mode on Windows, so deployments that assume TCC need to use WDDM or the compute-only MCDM mode instead. cuBLAS, the matrix-math library, gets updated heuristics and kernel tuning that NVIDIA says improve NVFP4 and MXFP8 matrix multiplication on Vera Rubin, including the shapes used to train mixture-of-experts models, but the post gives no figures.

Much of the rest of the release concerns dividing one GPU among workloads. A GPU's compute is organized into streaming multiprocessors (SMs), and CUDA can split them into partitions per locality domain. By default, those partitions get the same guaranteed SM count in every domain, and any extra SMs sit outside them. A new flag lets each selected domain include its extra SMs, so an application can use every SM on the device at the cost of partitions that may differ in size, and a discovery mode in the partitioning API reports each partition's count so work can be split to match. The choice is between predictable, equal partitions and using all of the hardware.

The Multi-Process Service (MPS), which lets several processes run on one GPU at the same time, reaches version 3. Weighted timeslicing gives longer compute turns to the MPS servers that need them. SM partitions can now borrow capacity beyond their base allocation and lend their SMs while no clients are attached, and MPS takes borrowed capacity back before reassigning it. Cgroup-based routing maps a cgroup v2 subtree, the Linux mechanism a workload launcher can use to group processes, to an MPS namespace, so clients are sent to the right resource policy automatically, and an SM partition can be assigned once per namespace instead of through an environment variable on every client. A polling fallback reads memory usage directly when cgroup notifications are missing or unreliable, at some extra cost per eviction decision. CUDA 13.4 had already added per-workload memory limits to MPS, which NVIDIA uses for fractional GPU sharing in Kubernetes.

For kernel authors, CUDA Tile kernels can now read and write memory on other GPUs connected by NVLink, with multicast operations on NVSwitch fabrics, so communication and computation can be combined in one kernel. A public preview lets Tile kernels call device functions from conventional SIMT libraries such as NVSHMEM and the MathDx libraries. The preview covers only library functions; calling your own device functions is planned for a later release, and NVIDIA says each library will enable the interop soon. The CCCL 3.5 libraries add a batched Top-K selection, an operation used to pick tokens during text generation, which NVIDIA says is already integrated into the FlashInfer inference kernel library, along with run-to-run reproducible floating-point scans on the same GPU, input and build.