Is SMIC N+3's Metal Pitch Smaller than Intel 18A's?
Source
STEEL Team
Author
STEEL Team
Date
Key takeaways · AI-distilled
SMIC N+3's 32.5nm minimum metal pitch is about 10% tighter than the 36nm in Intel's 18A Panther Lake. True but cherry-picked: N+3 buys that pitch with aggressive DUV multi-patterning, which costs process maturity, yield and cost per wafer.
Without EUV lithography, SMIC still reaches TSMC N6-class logic density using multi-patterning plus design-technology co-optimization. Density is reachable through effort; efficiency is not, and the efficiency gap is far wider than the performance gap.
The Kirin 9030 Pro performs like a three-year-old Android flagship. Apple's efficiency core delivers 20% higher integer performance than Huawei's prime core while drawing 1W against 4.5W, a roughly 4x power difference on the same work.
The 9030 kept nearly the same ~140mm2 die as the 9020 and spent the shrink on capability: a fourth middle core, 20% more shared L3, double the tiny-cluster L2. Per-core area fell about 22% while total cluster area barely moved.
Per-clock integer gains of 17% on the middle core and 14% on the tiny core came at flat or lower frequencies, which means microarchitecture, not process; a shrink alone cannot buy IPC. Both cores still failed to hold their rated peak clocks.
Why it matters
For engineers tracking global AI compute capacity and export-control impacts, this gives concrete, image-backed evidence of how close SMIC's DUV-based N+3 process actually comes to TSMC/Intel leading-edge nodes — intelligence that shapes expectations about future AI chip supply from China.
Key quotes
“SMIC has not overtaken Intel or TSMC.”
“Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path.”
