• Cerebras addressed memory-bandwidth limits with its Wafer-Scale Engine: hundreds of thousands of cores and tens of gigabytes of on-chip SRAM on one piece of silicon, at the cost of high energy consumption.
• Groq's compute-near-memory design distributes a network across chips with local SRAM and uses a deterministic dataflow architecture to strip out the non-deterministic control-flow overhead general-purpose processors carry, prioritizing latency.
• Nervana (2014) pioneered a low-precision FlexPoint numerical format for distributed matrix multiplication in neural-network chips; GPU makers validated the specialization by adopting similar approaches by 2017.
• Google's TPU pairs massive interconnected Matrix Multiplier Units arranged as a systolic array with high-bandwidth memory to cut instruction overhead, built specifically to serve Google's own in-house models rather than as a general accelerator.
• As a working example of its 'time as a first-class citizen' framing, the piece shows a steerable, trainable system built from a simulation of a physical dynamical system, trained to follow a target state-space trajectory over time.

• articleSystem Modeling: The Substrate for Neural Co-Evolution

• articleSystem Modeling: The Substrate for Neural Co-EvolutionCarlos H. Morales
• clipComputers-in-the-90s analogy for AI adoptionClaude
• articleIntroducing Sakana AI’s Frontier Intelligence Group (FIG)Sakana AI

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