Huaweis Roadmap To 2031

Epoch AI researcher Venkat Somala concludes that Huawei is unlikely to catch up to NVIDIA in AI compute by 2030, and that the reason shifts over time: today Huawei is mostly short of memory, but by 2028 the constraint starts moving toward how much each of its chips can compute (epoch.ai). Total compute is chip count multiplied by per-chip performance, and Huawei trails on both. Epoch's median estimate is 1.5 million Ascend units in 2026 against 5.9 million Nvidia chips, and on paper Nvidia's B300 delivers 13.5 PFLOPS at 4-bit precision versus 2 PFLOPS for Huawei's Ascend 950, roughly a 7x gap. Those compound to roughly 26x less compute: about 880,000 H100-equivalents for Huawei versus 23 million for Nvidia, under 4% of Nvidia's output. The report notes this is an on-paper comparison and that Huawei's realized performance is likely lower still, because its CANN software stack is far less mature than Nvidia's CUDA.

Volume is capped by high-bandwidth memory (HBM), the stacked DRAM that sits beside a chip's logic die and feeds it data fast enough to keep its arithmetic units busy. Chinese firms stockpiled more than 10 million foreign HBM stacks before the December 2024 export controls, and Epoch expects that stockpile to run out in 2026. After that, Huawei depends on what domestic makers CXMT and XMC produce and what can be smuggled in. Using only Chinese-made HBM, Epoch estimates Huawei's output could stay around 1% of Nvidia's through 2028. Even an implausibly large smuggling flow of ten times Huawei's domestic supply in 2028, which the report prices at over $40 billion, would lift output only to about 16% of Nvidia's. Huawei is already designing around the shortage: the Ascend 950PR likely uses lower-bandwidth, LPDDR-like memory and is aimed at prefill, the compute-heavy first stage of inference that suffers least from slower memory. SemiAnalysis identified HBM as Huawei's bottleneck in September 2025, and Epoch builds on its stockpile and CXMT estimates.

As China's HBM production ramps, Epoch's model shows the memory gap shrinking while the chip gap widens. Nvidia's advantage in usable HBM falls from 73x in 2026 to 11x in 2028, but its advantage in compute paired with each gigabyte of memory grows from 2.7x to 6.1x. The cause is manufacturing: export controls on advanced lithography leave Huawei's foundry, SMIC, at 5 to 7 nm-class processes through the decade, with roughly half the transistor density of TSMC's leading nodes. Huawei's roadmap projects a 7x compute gain from the Ascend 950 to the Ascend 970 in late 2028, but that must come from larger dies, more dies per package and a shift toward 4-bit arithmetic, which Epoch calls "a packaging and architecture roadmap rather than a process-node roadmap." Nvidia is pulling the same levers from a denser starting point. Huawei's strongest card is scale: SuperPoD systems linking up to 8,192 chips versus Nvidia's 72-GPU racks. Epoch notes those pods cannot give every chip full bandwidth to every other chip, that Huawei does not publish the metrics needed to judge them, and that scale-up is not a substitute for closing the per-chip gap.

Huawei's long-term answer is LogicFolding, stacking logic dies vertically so a 5 nm-class process can pack more transistors into the same footprint. Its folded 2026 Kirin phone chip reportedly gained 54% in density, cut power by 41% and raised peak clock speed by 13%, and Huawei targets 1.4 nm-equivalent density by 2031. But the first Ascend chip to use it is not due until 2030, while Nvidia's Feynman, expected in 2028, reportedly stacks dies made on TSMC's 1.6 nm-class process. Even under an optimistic 2030 memory scenario, Epoch's central estimate of 24 million H100-equivalents for Huawei is about what Nvidia ships in 2026, leaving it roughly four years behind on volume as well as per-chip performance. The report allows that Huawei may eventually catch up, but says the available information makes that unlikely by 2030.