SemiAnalysis
1 Tool · 61 Intel
SemiAnalysis is an independent research and analysis publication covering the semiconductor and AI industries, from chip design and fabrication to datacenters and AI infrastructure. Founded by Dylan Patel, it grew from a solo newsletter into a research firm with institutional consulting and custom modeling services for semiconductor companies and investors. Its reporting is widely followed in the chip industry, drawing public acknowledgment from figures like Nvidia CEO Jensen Huang and AMD CEO Lisa Su, and its newsletter counts hundreds of thousands of subscribers.
Is this you? Sign in with X to claim this profile.
Tools
Continuously re-benchmarks LLM inference across vLLM, SGLang and NVIDIA/AMD hardware weekly.
Intel
SemiAnalysis metered the $200/month plans against API list prices: roughly $8,000/month of tokens from Anthropic and up to $14,000 from OpenAI if you exhaust the weekly limits on long-horizon work. The test dates to June, so treat the ceilings as a snapshot rather than current policy.
SemiAnalysis unmasks the Ox Alpha model as GLM-5.3-Flash and reports that all of its roughly 100 trillion tokens per day of free serving ran on domestic Chinese chips, at hardware efficiency and per-token cost they put on par with Nvidia GPUs — another stress test of the CUDA moat.
SemiAnalysis lays out the cost case pulling hyperscalers to India: roughly $5M per MW of datacenter capex and power often under $0.10/kWh, cheap enough to put the country near 10GW by 2030 and among the four largest datacenter markets, with Microsoft alone committing $17.5B.
SemiAnalysis flags a 50 percent OpenAI price cut on GPT-5.6 Sol limited to two gateways, and argues the venues were picked because they are the datasources most used to estimate model market share.
SemiAnalysis argues SpaceX reaches ~10GW of datacenter capacity by end-2027, resting on inference economics of roughly $100B/GW/year in API revenue against ~$12B/GW/year of rental cost — and names Microsoft, with OpenAI model access and no training costs, as the other winner.
SemiAnalysis reports Nvidia Rubin Ultra will carry 192GB of HBM4 8-hi, down from the 1TB previewed and below Rubin's 288GB. The cut came from dropping the four-die part, shorter stacks, and 24Gb HBM4 dies. Nvidia's rationale is not given in the thread, and the claim is not confirmed by Nvidia.
SemiAnalysis on GLM-5.3 beating every American open model with gains that came entirely from post-training on the same base as GLM-5.2, and what that says about the Nemotron committee path.
SemiAnalysis reports measuring OpenAI's Jalapeño accelerator at up to 2x Nvidia's July Rubin performance per watt, and ahead across the entire Pareto curve — reportedly without speculative decoding enabled, against a Rubin NVL72 configuration that had it on.
SemiAnalysis reworks the Morgan Stanley ROIC framework that Nadella cited for token-as-a-service, arguing the $23/W IT capex assumption is far too low, that two errors happened to offset into roughly the right answer, and that ~$43/W invested capital is the more defensible baseline.
SemiAnalysis reports AMD's MI355X on vLLM beating NVIDIA's B200 on Kimi K2.5 using upstream AMD kernels from the GPU MODE community.
SemiAnalysis's AgentX inference benchmark on the 2.8T-parameter Kimi K3 model finds AMD's MI355X earning better profit margins per gigawatt (53.6%) than Nvidia's GB200 NVL72 (44.3%), attributed to lower total cost of ownership.
SemiAnalysis outlines three disaggregated inference setups for NVIDIA's LPU alongside Rubin: LPU decode, LPU FFN decode, and LPU drafting. Raw Rubin still wins at low interactivity, and GPTOSS 2T is a proxy config for closed frontier models.
SemiAnalysis on DeepSeek V4 Pro 0813 massively beating Nemotron3 Ultra on agentic tasks, and the argument that committee-based frontier model development fundamentally does not work.
SemiAnalysis traces Google's TPU interconnect from 2D torus on TPUv2 to 3D on v4/v5p and Boardfly on v8i, then walks the rumored 6D torus for TPUv9t: 12 ICI links per chip, worst-case hops on 4,096 chips cut from 24 to 12, paid for in far more optics.
SemiAnalysis argues Nvidia cut Rubin Ultra from HBM4E 12-Hi (384GB) to HBM4 8-Hi (192GB) because memory had reached about 40% of rack capital cost. The cut lowers that to about 28% and shifts spend to scale-up optics, which it reads as a sign of continued supply shortage.
SemiAnalysis walks through Cerebras CS-4: doubled off-wafer I/O, an upgradeable Ethernet-translating NIC, and disaggregated inference pairing wafers for decode with HBM chips like AMD and Trainium for prefill. Based on the thread only; the full article was not read.
SemiAnalysis puts GB300 NVL72 at 7x the performance per dollar of H200 for long-context agentic inference, crediting disaggregated prefill and wide expert parallelism that the NVL72 copper backplane makes possible — serving architecture rather than silicon doing the work.
SemiAnalysis breaks down record 2Q26 foundry revenue of $54.5B driven by pricing and mix rather than capacity. Covers N3 as the AI bottleneck, TSMC's HPC share, mature-node price increases, Samsung and Intel foundry moves, and record capex. Based on the thread only, not the underlying model.
SemiAnalysis contrasts NVIDIA Research's influence, LatentMoE in Kimi K3 and GatedDeltaNets in Qwen, with its own frontier training results: Nemotron3 Ultra at 550B total and 55B active parameters is losing to Chinese models roughly 20x smaller.
SemiAnalysis compares OpenAI's Jalapeño with Nvidia's Vera Rubin July results. It sees a win on output throughput per megawatt, rough parity on performance per TCO with upside from speculative decoding, and Codex assisting chip block design and kernel tuning.
SemiAnalysis reports that AMD merged code into NVIDIA's NIXL inference communication library in June 2026, deprecated its RIXL fork, and now lands changes upstream, ending monthly fork syncing. Merge evidence was not independently verified.
SemiAnalysis mines 2.91M Claude tool-use responses for how operating systems shape agentic AI, finding Linux runs shell commands roughly three times faster than Windows.
SemiAnalysis details Huawei's Atlas 950 SuperPoD: 16 racks of 64 Ascend 950 NPUs, 1 EFLOPS FP8, 98TB of HiZQ memory, a backplane 2D mesh with low-radix switches, and 800G LPO pluggables that drop optical DSPs to cut cost and power.
SemiAnalysis itemizes the architecture Qwen previews in 3.8-Flash-Next ahead of Qwen4: a 51-billion-parameter n-gram embedding table cheap enough to push onto slower DRAM tiers, gated residual connections, and a lightning indexer selecting context at micro-block granularity.